Design of Baugh-wooley Multiplier using Verilog HDL. Shruti D. Kale, Prof. Gauri N. Zade. India. Abstract: Multiplication represents one of the major holdups in. Adders and Multipliers. Baugh-Wooley Multiplier Design • To illustrate the mathematical transformation which is required, consider 4-bit signed operands X and. This project presents an efficient implementation of a high speed multiplier using the shift and adds method of. Baugh-Wooley Multiplier.

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Received 18 April ; accepted 15 May ; published 15 June This paper provides the design of compact Baugh-Wooley multiplier using reversible logic. Even though various researches have been done multiplifr designing reversible multiplier, this work is the first in the literature to use Baugh-Wooley algorithm using reversible logic. Gaugh reversible multiplier cell is useful in building up regularity in the array multipliers.

The Toffoli gate synthesis of the proposed reversible multiplier cell is also given.

Design of Compact Baugh-Wooley Multiplier Using Reversible Logic

As the nano devices are developed, the density of digital chips is being increased naturally seeking the solution for the power consumption and the heat dissipation developed by this power consumption. This scenario motivates the study of reversible computing field. The origin of the reversible computing is the research work done by R. A circuit will be known as reversible if it can bring back the inputs from the outputs.

Also the relationship between the inputs and outputs should be maintained as one-to-one and unique. This constraint forces the number of inputs to be equal to the number of outputs [3] [4]. The quantum circuits can be constructed only with reversible logic gates. Besides, synthesizing reversible logic circuits is much difficult than conventional irreversible logic circuits due to the constraints.

In the reversible logic circuit design, fan-out and feedback are not permitted [4]. Apart from that the reversible logic circuit should use 1 lowest number of reversible gates, 2 lowest number of garbage outputs, 3 lowest number of constant inputs.

The garbage output is the one which is not used for further computations. The additional input that is included to the irreversible function to convert it reversible is called constant input [4]. In the recent years various reversible multiplier designs have been proposed [5] – [9].

It has been done in two steps as follows: To generate the partial products, 16 Peres gates have been used, for 16 one-bit multiplication arrays. Then the four operand addition has been performed using Peres gates and Double Peres gates. In [6]the authors have proposed a new reversible gate called as HNG gate.

This work also involves two steps as in [5].

The partial products have been generated using Peres gates. HNG gates are used in the second step, Multi operand addition. The work [7] also follows the same strategy as the previous two works, multiplication in two steps.

In this work also, like the previous works, the partial products have been generated using Peres gate. The PFAG gate is used in the multi operand addition. In [8]the authors have proposed a new reversible gate called as RAM gate. This gate is mainly used as a copying gate as fan-out is not allowed in reversible logic design.


This gate has been used in the partial product generation. In the second step, the multi operand addition, Peres gates and Dooley Peres gates have been used. In our work, we have proposed a reversible multiplier cell which can be efficiently used in the Baugh Wooley multiplier.

The organization of the paper is as follows. Section 2 is an overview of basic reversible gates. Section 3 is an multplier of Baugh-Wooley multiplier.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog – Semantic Scholar

A detailed representation and explanation is done in this section. The proposed reversible multiplier design and its functions are discussed in section 4. The results and discussions of the proposed reversible Baugh-Wooley multiplier are presented in section 5. Multiplker is in section 6. This constraint forces the number of inputs to be equal to the number of outputs. This section deals with the preliminary reversible gates available in the literature.

Feynman Gate FG can be used as a copying gate. Since in reversible circuits the fan-out greater that one is not permitted, this gate is useful for duplicating the inputs. This gate is also known as Controlled-Not gate. The number of inputs and outputs are three in count; if the first two bits A and B are set, the third bit will be inverted, otherwise all jultiplier will keep buagh the same value.

Hence this is also called as Swap gate. Function wise Peres Gate will be equal with the bit conversion generated wooly a Toffoli Gate succeeded by a Feynman Gate. One of the efficient algorithms to handle such situation is the Baugh-Wooley multiplication. Let the numbers to be multiplied be A and B. The multiplier A and the multiplicand B can be represented as. The final product could be generated by subtracting the last two positive terms from the first two terms. As a first step pad each of the last two terms in the product P with zeros to obtain a 2n-bit number to aid adding it with the other terms.

Let X be mulgiplier of the last two terms that can represent it with zero padding as. The block diagram representation of 4 bit Baugh-Wooley multiplier is shown in Figure 5. In the block diagram shown in Figure 5three types of cells are used. The yellow cells represent the full adder.

Block diagram of 4-bit Baugh-Wooly multiplier. The grey cells represent the multiplier cell. Each of the multiplier cell receives four inputs namely, the multiplier input horizontal-green linemultiplicand input vertical-red linecarry from previous cells vertical-black line and sum from previous cells diagonal-black line.

They produce two outputs namely sum output diagonal-black line and carry output vertical black line. In this work we are proposing two reversible multiplier cells representing black and grey cells.

A Fixed-Width Modified Baugh-Wooley Multiplier Using Verilog

Since each cell is having four inputs and two outputs, the reversible multiplier cell, in order to maintain the reversible constraints it is developed as a cell having five inputs and five outputs. Out of this, three outputs are maintained as garbage outputs.

Out of the five outputs, two outputs Q and R are left unspecified, since these are the garbage outputs. The functions S and T will produce sum and carry outputs respectively. The representation has the Gate Count of The Quantum cost is The number of two-Qubit gates is The functions S and T will produce sum and carry outputs respectively of the complement function of the Baugh- Wooley structure.

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Reversible multiplier cell MC. Synthesis of reversible multiplier cell. These proposed multiplier cells are having one constant input. The input A is the multiplier bit. The input B is the multiplicand bit. The input C is the carry input from the previous cells. The input D is the sum input from the previous cells. The outputs P, Q and R are considered as garbage outputs.

Since this is an incompletely specified reversible logic gates the functions Q and R are not specified. The reversible multiplier designs available in the literature are for the array multipliers.

There is no any specific application of any algorithm except [15]. However this work is compared and evaluated with the other array multiplier designs available in the literature. Therefore the proposed multiplier cells are evaluated based on the Gate count, Garbage inputs and Garbage outputs. Since the proposed cells are incompletely specified cells we could not generate the Quantum cost and therefore we could not evaluate the proposed baugb based on the Quantum cost.

Measuring the reversible logic design in terms of number of gates is one of the major factors. In [5]the design requires a total of 40 reversible gates, [9] wooleey 42, total number of gates required is 44 in [7] and in [8] the number of gates required is 32 gates. The proposed Baugh-Wooley multiplier design requires 20 gates.

Therefore, the hardware intricacy of the proposed design is less compared to the existing approaches. One of the major factors in the design of a reversible logic circuit is the number of constant inputs. The proposed reversible Baugh-Wooley multiplier design requires 16 constant inputs, but the design in [5] [7] – [9] requires 52, 40, 44 and 42 respectively. Hence the proposed Baugh- Wooley Multiplier design is better than existing designs.

The number of output of the reversible gate that is not making useful functions is referred as garbage output. Other constraint in designing reversible logic circuit is optimizing garbage outputs. The proposed reversible Baugh- Wooley multiplier design produces 48 garbage outputs, but the design in [5] [7] – [9] produces 52, 52, 40 and 49 garbage outputs respectively.

Therefore, it is clear that this is baugg better design than the existing counterparts. The conclusion of the above discussion is that, it multoplier evident that the proposed reversible Baugh-Wooley multiplier circuit design is better bahgh the existing designs with respect to gate counts, garbage inputs and garbage outputs. The proposed reversible Baugh-Wooley multiplier circuit is more efficient compared to the existing circuits presented by [5] [7] – [9].

This can be understood easily with the help of the comparison results shown in Table 1. These reversible multiplier cells are targeted for reversible Baugh-Wooley multiplier design.